1. Field of the Invention
Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of an amorphous carbon layer on a semiconductor substrate.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors and resistors on a single chip. The evolution of chip design continually requires faster circuitry and greater circuit density. The demand for faster circuits with greater circuit densities imposes corresponding demands on the materials used to fabricate such integrated circuits. In particular, as the dimensions of integrated circuit components are reduced to sub-micron dimensions, it has been necessary to use not only low resistivity conductive materials such as copper to improve the electrical performance of devices, but also low dielectric constant insulating materials, often referred to as low-k dielectric materials. Low-k dielectric materials generally have a dielectric constant of less than 3.8.
Producing devices having low-k dielectric materials with little or no surface defects or feature deformation is problematic. Low-k dielectric materials having a dielectric constant less than about 3.0 are often porous and susceptible to being scratched or damaged during subsequent process steps, thus increasing the likelihood of defects being formed on the substrate surface. Such low-k dielectric materials are often brittle and may deform under conventional polishing processes, such as chemical mechanical polishing (CMP). One solution to limiting or reducing surface defects and deformation of such low-k dielectric materials is the deposition of a hardmask over the exposed low-k dielectric materials prior to patterning and etching. The hardmask prevents damage and deformation of the delicate low-k dielectric materials. In addition, a hardmask layer may act as an etch mask in conjunction with conventional lithographic techniques to prevent the removal of the low-k dielectric material during etch.
Additionally, hardmasks are being used for almost every step in integrated circuit manufacturing processes for both front-end and back-end processes. As device sizes shrink and pattern structure becomes more complex and difficult to manufacture, an etch hardmask is becoming more important as available photoresists are failing to meet the etching resistance requirements and photoresists are simply being used for image transfer rather than as an etch mask in a lithography and etching process. Instead hardmasks that receive the image pattern are becoming the primary material for effective etching of patterns in underlying layers.
Amorphous hydrogenated carbon is a material that may be used as a hardmask for metals, amorphous silicon, and dielectric materials, such as silicon dioxide or silicon nitride materials, among others. Amorphous hydrogenated carbon, also referred to as amorphous carbon and may be denoted as a-C:H or α-C:H, is considered a carbon material with no long-range crystalline order and which may contain substantial hydrogen content, for example on the order of about 10 to 45 atomic % of hydrogen. Amorphous carbon has been observed to have chemical inertness, optical transparency, and good mechanical properties. While a-C:H films can be deposited via various techniques, plasma enhanced chemical vapor deposition (PECVD) is widely used due to cost efficiency and film property tunability. In a typical PECVD process, a hydrocarbon source, such as a gas-phase hydrocarbon or a liquid-phase hydrocarbon that has been entrained in a carrier gas, is introduced into a PECVD chamber. Plasma is then initiated in the chamber to create excited CH— radicals. The excited CH— radicals are chemically bound to the surface of a substrate positioned in the chamber, forming the desired a-C:H film thereon.
For applications in which a hardmask layer is deposited on a substrate having topographic features, the hardmask layer is required to conformally cover all surfaces of said topographic features. Additionally as feature sizes are reduced, photoresists materials have trouble correctly transferring patterns due to the limitation of light wavelengths and pattern sizes. As such, new processes and material are becoming required to address these challenges, of which hardmasks are becoming critical to the effective transfer of critical dimension for the next generation devices.
Hardmask layer deposition conformality is difficult to achieve on a substrate with an underlying topography, for example an alignment key used to align the patterning process. FIG. 1 illustrates a schematic cross-sectional view of a substrate 100 with a feature 111 and a non-conformal amorphous carbon layer 112 formed thereon. Because non-conformal amorphous carbon layer 112 does not completely cover the sidewalls 114 of feature 111, subsequent etching processes may result in unwanted erosion of sidewalls 114. The lack of complete coverage of sidewalls 114 by non-conformal amorphous carbon layer 112 may also lead to photoresist poisoning of the material under non-conformal carbon layer 112, which is known to damage electronic devices.
Therefore, there is a need for a method of depositing a material layer useful for integrated circuit fabrication which can be conformally deposited on substrates having topographic features.